This application is based upon and claims priority from prior European Patent Application No. 00830869.4, filed Dec. 29, 2000, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to electronic circuits, and more specifically to a generator circuit for voltage ramps having improved dynamic operation and a corresponding voltage generation method.
2. Description of Related Art
As is known, in the last generation EEPROM memories, either of the xe2x80x9cgeneral purposexe2x80x9d or of the xe2x80x9cembeddedxe2x80x9d types, two fundamental specifications, that are a reduction of the writing time and a greater reliability of the whole memory device, are required.
In particular, in the memories that use the method of Fowler-Nordheim for writing the cells, these two needs are actually in contrast with each other. In fact, in order to guarantee a certain reliability degree, in terms of time of keeping the information and of maximum number of writing cycles allowed, the cell is programmed by a ramp voltage pulse with a slope such to guarantee a control of the highest peak of the Fowler-Nordheim current that goes trough the tunnel oxide layer of the cell.
It is in fact known that such a current peak, that is the main responsible of the decay of a memory cell, is directly co-related to the ramp slope of the programming voltage.
For this reason, in this field ramp generators are very important and they have to be projected in order to guarantee a good control of the voltage slope apart from the output load.
In particular, the programming pulse shown in the FIG. 1 shows a first line, starting from an initial time T*xe2x88x92xcex94T* with a duration of xcex94T*, showing a ramp pattern with a first high slope and a second line, starting from a time T* for a duration equal to a Tr*, having a ramp pattern with a second slope lower than the first slope. It is also provided a third line at a null slope for a total duration equal to Tr.
The voltage value Vp of such a programming pulse goes from an initial value conventionally equal to 0 to a first value equal to Vs during the first portion of the ramp in order to reach and maintain a top value equal to Vtop during the second portion of the ramp, while the third portion is constant with the top value Vtop.
The use of this double ramp pulse drastically reduces the duration of a first programming step. In fact during such a first phase the Fowler-Nordheim tunneling has not shown out yet or is still of negligible entity and the pulse voltage Vp is maintained below a triggering voltage Vfnt of such a tunneling. The same programming pulse appears then with a second slope efficient for a second programming phase that still uses the Fowler-Nordheim tunneling; in this case, the pulse voltage Vp reaches greater values than the triggering voltage Vfnt.
As far as the EEPROM memory is concerned, typical values are considered which are equal to the following.
xe2x80x83Vs=6 to 8V
Vtop=11 to 15V
Tr=0.5 to 1 ms
Slopes allowed to the second part of the ramp  less than 20 V/ms.
In order to obtain significant time reductions, the first part of the programming voltage ramp Vp must indeed have slopes higher than 50 V/ms.
A ramp generator projected in order to provide such a double ramp pulse must therefore control suitable currents, keeping into consideration that the loads to be driven in the global programmings of whole selected memory matrixes result in being in the order of nanofarads.
A further complication in projecting such ramp generators derives from the necessity of reducing the top values operated inside the generators by means of the memory devices in order to face up to the scaling effects deriving from the use of a more and more reduced integration geometry.
This need imposes the use of lower and lower boosted voltage levels and also the project of ramp generators that use the top voltage available inside the memory device as much as possible.
A typical ramp generator of the known type, used to generate a double ramp programming pulse for memory cells of the EEPROM type, is schematically shown in FIG. 2.
The ramp generator 1 comprises an operational amplifier 2 supplied by a first supply voltage reference HVP, in particular a voltage HVP generated by means of a booster incorporated in the memory device that is not illustrated since it is conventional. The first voltage reference HVP coincides to the top voltage available inside the memory device.
The operational amplifier 2 also shows a first inverter input terminal IN1, on which a first reference voltage Vref and a second non-inverter input terminal IN2, receiving a second internal voltage BOT, are applied.
Such a reference Vref voltage is generated for example by means of a Bandgap circuit (that is also not illustrated since it is conventional).
An output terminal of the operational amplifier 2 is connected to a control terminal of a MOS transistor M1 of the P type, that is in turn inserted between the first voltage reference HVP and an output terminal OUT of the ramp generator 1.
The output terminal OUT of the ramp generator 1 is further connected to a second voltage reference, particularly to a GND through the series of a first capacitor C1 and a current I1 generator G1. Between the output terminal OUT and the GND there is also a second load capacitor C2.
The interconnection node X1 between the first capacitor C1 and the generator G1 is feedback connected to the second non-inverter input terminal IN2 of the operational amplifier 2.
The second capacitor C2 substantially corresponds to the load seen by the ramp generator 1, the value of which particularly depends on the number of bytes selected in the memory matrix to be programmed.
The current generator G1 is indeed obtained by a reference value already available inside the memory device and can be varied by means of suitable mirror current relations in order to obtain the first and the second required slopes. In fact, the output voltage Vout of the ramp generator 1 shows a ramp pattern having a slope equal to the following.
Slope=I1/C1
It should be noted that the ramp generator 1 has a first amplification stage S1, essentially comprising the operational amplifier 2 and a second output stage S2 comprising the transistor M1, the capacitors C1 and C2 and the generator G1.
Particularly, the first amplification stage S1 biases, by means of a virtual short circuit, the current generator G1 so that:
dVout/dt=I1/C1xe2x88x92dV1/dt=I1/C1=K
with Vout being the output voltage of the ramp generator 1; V1 being the potential present at the terminal X1; and K being the required slope.
Indeed, the output stage S2 operates a voltage/current conversion. In particular, the use of the MOS transistor M1 of the P type in the output stage S2 allows a suitable gm transconductance value to be obtained, as well as a regulation of the loop gain of the set operational amplifier 2/ transistor M1/ capacitor C1, thanks to the amplification of the first stage S1, so that the maximum value of the voltage ramp produced by the generator G1 and by the first capacitor C1 is exactly equal to the top voltage value of the memory device.
Although it is advantageous under many points of view, this first solution shows many drawbacks, particularly the one of stabilization in frequency.
In fact, the sizing of single components of the ramp generator 1 must be taken keeping into consideration of an Iout current, to be operated by the output terminal OUT, given by the following
Iout=C2(dVout/dt)
Such sizing must also provide a suitable phase margin in order to guarantee the ramp generator 1 stability in case of variability during its manufacturing process, as well as depending on the operation temperature range of the same, on the supply voltage range and on the applied load variations.
All this causes a great manufacturing difficulty and the sizing of the ramp generator 1 according to the prior art.
In fact, because of the extended variability of the parameters, even a simulated phase margin of 35 degrees could not guarantee the necessary safety in terms of generator stability as a whole. It is suitable to note that such a phase margin can only be obtained with a great waste of area (so called compensation with dominant pole) or with factors PSRR unsuitable for the type of application (so called zero-pole compensation).
A second known solution provides the use of an output stage S2 of the voltage follower type, that is a stage that uses an output MOS transistor of the N type.
In such a way an intrinsically steady ramp generator 1 is obtained, and also an output Voltage Vout of a maximum value invalidated by a threshold voltage value of a transistor of the N type, that is a value lower than the one predetermined or desired for a correct memory cells programming.
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide an improved double ramp voltage generator (e.g., for programming memory cells). A preferred embodiment of the present invention provides a generator circuit for voltage ramps that includes a differential stage with positive feedback, having an output connected to the control terminal of a first output transistor connected to a capacitive load to be biased with voltage ramps. The present invention also provides a method for generating voltage ramps in biasing circuits of capacitive loads for memory devices, of the type in which the load receives a double ramp voltage signal with a first predetermined slope and a second slope lower than the preceding one.
Another object of the present invention is to use a first output stage showing a mixed structure with a pair of transistors, PMOS and NMOS, each activated at a corresponding portion of the voltage ramp.
One embodiment of the present invention provides a generator circuit for voltage ramps is provided that includes a differential stage with positive feedback coupled between a first and a second voltage reference and having a first output connected to a control terminal of a first output transistor. The first output transistor is connected at an output terminal of the ramp generator circuit to a capacitive charge to be biased with voltage ramps. The ramp generator circuit also includes a second output transistor parallel connected to the first output transistor and having the control terminal connected to a second output of the differential stage.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.